\doxysection{C\+:/\+Users/\+ASUS/\+Desktop/dm-\/ctrl\+H7-\/balance-\/9025test/\+Drivers/\+STM32\+H7xx\+\_\+\+HAL\+\_\+\+Driver/\+Inc/stm32h7xx\+\_\+hal\+\_\+pwr.h File Reference}
\hypertarget{stm32h7xx__hal__pwr_8h}{}\label{stm32h7xx__hal__pwr_8h}\index{C:/Users/ASUS/Desktop/dm-\/ctrlH7-\/balance-\/9025test/Drivers/STM32H7xx\_HAL\_Driver/Inc/stm32h7xx\_hal\_pwr.h@{C:/Users/ASUS/Desktop/dm-\/ctrlH7-\/balance-\/9025test/Drivers/STM32H7xx\_HAL\_Driver/Inc/stm32h7xx\_hal\_pwr.h}}


Header file of PWR HAL module.  


{\ttfamily \#include "{}stm32h7xx\+\_\+hal\+\_\+def.\+h"{}}\newline
{\ttfamily \#include "{}stm32h7xx\+\_\+hal\+\_\+pwr\+\_\+ex.\+h"{}}\newline
\doxysubsubsection*{Classes}
\begin{DoxyCompactItemize}
\item 
struct \mbox{\hyperlink{struct_p_w_r___p_v_d_type_def}{PWR\+\_\+\+PVDType\+Def}}
\begin{DoxyCompactList}\small\item\em PWR PVD configuration structure definition. \end{DoxyCompactList}\end{DoxyCompactItemize}
\doxysubsubsection*{Macros}
\begin{DoxyCompactItemize}
\item 
\#define \mbox{\hyperlink{group___p_w_r___p_v_d__detection__level_gaddf4616a143ac3481f3043f2a4c21c18}{PWR\+\_\+\+PVDLEVEL\+\_\+0}}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga9f90ed5fb8f7820030d4af6dd328e878}{PWR\+\_\+\+CR1\+\_\+\+PLS\+\_\+\+LEV0}}
\item 
\#define \mbox{\hyperlink{group___p_w_r___p_v_d__detection__level_ga06e55b20a8777594f1a91ee71fac1f79}{PWR\+\_\+\+PVDLEVEL\+\_\+1}}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga7c408bce8836b7af46141cddcd6f20ac}{PWR\+\_\+\+CR1\+\_\+\+PLS\+\_\+\+LEV1}}
\item 
\#define \mbox{\hyperlink{group___p_w_r___p_v_d__detection__level_gab26bb78650bbaef26ac9f9123c791cc7}{PWR\+\_\+\+PVDLEVEL\+\_\+2}}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_gae3ecef9c0e7ba8ce56e16245bc71e08f}{PWR\+\_\+\+CR1\+\_\+\+PLS\+\_\+\+LEV2}}
\item 
\#define \mbox{\hyperlink{group___p_w_r___p_v_d__detection__level_ga7b751743b3e29c237e6a0e1d7bdd0503}{PWR\+\_\+\+PVDLEVEL\+\_\+3}}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga582890057e060cbf8a55109adf7e0de1}{PWR\+\_\+\+CR1\+\_\+\+PLS\+\_\+\+LEV3}}
\item 
\#define \mbox{\hyperlink{group___p_w_r___p_v_d__detection__level_ga03c0d3ae547deb1a51b8acafac101698}{PWR\+\_\+\+PVDLEVEL\+\_\+4}}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga3cd20cdf94731917fce93dfd4edbd779}{PWR\+\_\+\+CR1\+\_\+\+PLS\+\_\+\+LEV4}}
\item 
\#define \mbox{\hyperlink{group___p_w_r___p_v_d__detection__level_ga46a1476440945c2b6426b4973172f24b}{PWR\+\_\+\+PVDLEVEL\+\_\+5}}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_gaf62a1df94e4815553b9f4d7a0ba8d38d}{PWR\+\_\+\+CR1\+\_\+\+PLS\+\_\+\+LEV5}}
\item 
\#define \mbox{\hyperlink{group___p_w_r___p_v_d__detection__level_ga5dda7d0ac3fd3d606666455ca3c8f537}{PWR\+\_\+\+PVDLEVEL\+\_\+6}}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga9eb05102ebd0b1df9e1224e4dfa4f56f}{PWR\+\_\+\+CR1\+\_\+\+PLS\+\_\+\+LEV6}}
\item 
\#define \mbox{\hyperlink{group___p_w_r___p_v_d__detection__level_ga2c5cd8dd26b13bdf0164c1f7596b4bfd}{PWR\+\_\+\+PVDLEVEL\+\_\+7}}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_gac86012781b7d18d72e37caf8995cbe06}{PWR\+\_\+\+CR1\+\_\+\+PLS\+\_\+\+LEV7}}
\item 
\#define \mbox{\hyperlink{group___p_w_r___p_v_d___mode_ga3a4bf701a36a14a4edf4dc5a28153277}{PWR\+\_\+\+PVD\+\_\+\+MODE\+\_\+\+NORMAL}}~(0x00000000U)
\item 
\#define \mbox{\hyperlink{group___p_w_r___p_v_d___mode_ga102d7b8354419990a2a780f61cd020a6}{PWR\+\_\+\+PVD\+\_\+\+MODE\+\_\+\+IT\+\_\+\+RISING}}~(0x00010001U)
\item 
\#define \mbox{\hyperlink{group___p_w_r___p_v_d___mode_gab600a54f3a588de836cfe4b727ab8a53}{PWR\+\_\+\+PVD\+\_\+\+MODE\+\_\+\+IT\+\_\+\+FALLING}}~(0x00010002U)
\item 
\#define \mbox{\hyperlink{group___p_w_r___p_v_d___mode_gac531fbf14457e6595505354fad521b67}{PWR\+\_\+\+PVD\+\_\+\+MODE\+\_\+\+IT\+\_\+\+RISING\+\_\+\+FALLING}}~(0x00010003U)
\item 
\#define \mbox{\hyperlink{group___p_w_r___p_v_d___mode_ga1a946b01887aa886de329a92c3ab0dd4}{PWR\+\_\+\+PVD\+\_\+\+MODE\+\_\+\+EVENT\+\_\+\+RISING}}~(0x00020001U)
\item 
\#define \mbox{\hyperlink{group___p_w_r___p_v_d___mode_gaaedbe45f1a1ea6c30af6ac51abae0cae}{PWR\+\_\+\+PVD\+\_\+\+MODE\+\_\+\+EVENT\+\_\+\+FALLING}}~(0x00020002U)
\item 
\#define \mbox{\hyperlink{group___p_w_r___p_v_d___mode_ga7455387c8e9049f9f66b46423d4f4091}{PWR\+\_\+\+PVD\+\_\+\+MODE\+\_\+\+EVENT\+\_\+\+RISING\+\_\+\+FALLING}}~(0x00020003U)
\item 
\#define {\bfseries PWR\+\_\+\+MAINREGULATOR\+\_\+\+ON}~(0U)
\item 
\#define {\bfseries PWR\+\_\+\+LOWPOWERREGULATOR\+\_\+\+ON}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_gacc60f674740c4000a25b0e3e50ede47d}{PWR\+\_\+\+CR1\+\_\+\+LPDS}}
\item 
\#define {\bfseries PWR\+\_\+\+SLEEPENTRY\+\_\+\+WFI}~(0x01U)
\item 
\#define {\bfseries PWR\+\_\+\+SLEEPENTRY\+\_\+\+WFE}~(0x02U)
\item 
\#define {\bfseries PWR\+\_\+\+STOPENTRY\+\_\+\+WFI}~(0x01U)
\item 
\#define {\bfseries PWR\+\_\+\+STOPENTRY\+\_\+\+WFE}~(0x02U)
\item 
\#define {\bfseries PWR\+\_\+\+REGULATOR\+\_\+\+VOLTAGE\+\_\+\+SCALE0}~(0U)
\item 
\#define {\bfseries PWR\+\_\+\+REGULATOR\+\_\+\+VOLTAGE\+\_\+\+SCALE1}~(\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga6bb6c55fe5c72ab2fb75f12fccd9a032}{PWR\+\_\+\+D3\+CR\+\_\+\+VOS\+\_\+1}} \texorpdfstring{$\vert$}{|} \mbox{\hyperlink{group___peripheral___registers___bits___definition_gabea91864a518cdbc6ea132be6e6af4af}{PWR\+\_\+\+D3\+CR\+\_\+\+VOS\+\_\+0}})
\item 
\#define {\bfseries PWR\+\_\+\+REGULATOR\+\_\+\+VOLTAGE\+\_\+\+SCALE2}~(\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga6bb6c55fe5c72ab2fb75f12fccd9a032}{PWR\+\_\+\+D3\+CR\+\_\+\+VOS\+\_\+1}})
\item 
\#define {\bfseries PWR\+\_\+\+REGULATOR\+\_\+\+VOLTAGE\+\_\+\+SCALE3}~(\mbox{\hyperlink{group___peripheral___registers___bits___definition_gabea91864a518cdbc6ea132be6e6af4af}{PWR\+\_\+\+D3\+CR\+\_\+\+VOS\+\_\+0}})
\item 
\#define {\bfseries PWR\+\_\+\+FLAG\+\_\+\+STOP}~(0x01U)
\item 
\#define {\bfseries PWR\+\_\+\+FLAG\+\_\+\+SB}~(0x04U)
\item 
\#define {\bfseries PWR\+\_\+\+FLAG\+\_\+\+PVDO}~(0x0\+BU)
\item 
\#define {\bfseries PWR\+\_\+\+FLAG\+\_\+\+AVDO}~(0x0\+CU)
\item 
\#define {\bfseries PWR\+\_\+\+FLAG\+\_\+\+ACTVOSRDY}~(0x0\+DU)
\item 
\#define {\bfseries PWR\+\_\+\+FLAG\+\_\+\+ACTVOS}~(0x0\+EU)
\item 
\#define {\bfseries PWR\+\_\+\+FLAG\+\_\+\+BRR}~(0x0\+FU)
\item 
\#define {\bfseries PWR\+\_\+\+FLAG\+\_\+\+VOSRDY}~(0x10U)
\item 
\#define {\bfseries PWR\+\_\+\+FLAG\+\_\+\+SCUEN}~(0x11U)
\item 
\#define {\bfseries PWR\+\_\+\+FLAG\+\_\+\+USB33\+RDY}~(0x13U)
\item 
\#define {\bfseries PWR\+\_\+\+FLAG\+\_\+\+TEMPH}~(0x14U)
\item 
\#define {\bfseries PWR\+\_\+\+FLAG\+\_\+\+TEMPL}~(0x15U)
\item 
\#define {\bfseries PWR\+\_\+\+FLAG\+\_\+\+VBATH}~(0x16U)
\item 
\#define {\bfseries PWR\+\_\+\+FLAG\+\_\+\+VBATL}~(0x17U)
\item 
\#define {\bfseries PWR\+\_\+\+FLAG\+\_\+\+WKUP1}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_gab3f7106e80257d68575ec69d4ba3df1b}{PWR\+\_\+\+WKUPCR\+\_\+\+WKUPC1}}
\item 
\#define {\bfseries PWR\+\_\+\+FLAG\+\_\+\+WKUP2}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_gacff74d63fa86695d3eed64c759eb5bed}{PWR\+\_\+\+WKUPCR\+\_\+\+WKUPC2}}
\item 
\#define {\bfseries PWR\+\_\+\+FLAG\+\_\+\+WKUP3}~PWR\+\_\+\+WKUPCR\+\_\+\+WKUPC3
\item 
\#define {\bfseries PWR\+\_\+\+FLAG\+\_\+\+WKUP4}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga223b7bd00095a8b2e4fdaa8acb7e35d8}{PWR\+\_\+\+WKUPCR\+\_\+\+WKUPC4}}
\item 
\#define {\bfseries PWR\+\_\+\+FLAG\+\_\+\+WKUP5}~PWR\+\_\+\+WKUPCR\+\_\+\+WKUPC5
\item 
\#define {\bfseries PWR\+\_\+\+FLAG\+\_\+\+WKUP6}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_gae2163c159213a47b5aa6c498c8257e0c}{PWR\+\_\+\+WKUPCR\+\_\+\+WKUPC6}}
\item 
\#define {\bfseries PWR\+\_\+\+EWUP\+\_\+\+MASK}~(0x0\+FFF3\+F3\+FU)
\item 
\#define \mbox{\hyperlink{group___p_w_r___exported___macro_ga1ee778f7ff494723bd0ef04ec44b0f77}{\+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+VOLTAGESCALING\+\_\+\+CONFIG}}(\+\_\+\+\_\+\+REGULATOR\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em Configure the main internal regulator output voltage. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___p_w_r___exported___macro_ga2977135bbea35b786805eea640d1c884}{\+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+GET\+\_\+\+FLAG}}(\+\_\+\+\_\+\+FLAG\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em Check PWR flags are set or not. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___p_w_r___exported___macro_ga8e3eb6bbc85beee17d213d64e99e8eed}{\+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+GET\+\_\+\+WAKEUPFLAG}}(\+\_\+\+\_\+\+FLAG\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em Check PWR wake up flags are set or not. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___p_w_r___exported___macro_ga96f24bf4b16c9f944cd829100bf746e5}{\+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+CLEAR\+\_\+\+FLAG}}(\+\_\+\+\_\+\+FLAG\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em Clear CPU PWR flags. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___p_w_r___exported___macro_ga21189c3a699027e3e932dff6985b2516}{\+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+CLEAR\+\_\+\+WAKEUPFLAG}}(\+\_\+\+\_\+\+FLAG\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em Clear PWR wake up flags. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___p_w_r___exported___macro_ga3180f039cf14ef78a64089f387f8f9c2}{\+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+PVD\+\_\+\+EXTI\+\_\+\+ENABLE\+\_\+\+IT}}()
\begin{DoxyCompactList}\small\item\em Enable the PVD EXTI Line 16. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___p_w_r___exported___macro_gad240d7bf8f15191b068497b9aead1f1f}{\+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+PVD\+\_\+\+EXTI\+\_\+\+DISABLE\+\_\+\+IT}}()
\begin{DoxyCompactList}\small\item\em Disable the PVD EXTI Line 16. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___p_w_r___exported___macro_gae5ba5672fe8cb7c1686c7f2cc211b128}{\+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+PVD\+\_\+\+EXTI\+\_\+\+ENABLE\+\_\+\+EVENT}}()
\begin{DoxyCompactList}\small\item\em Enable event on PVD EXTI Line 16. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___p_w_r___exported___macro_ga8bd379e960497722450c7cea474a7e7a}{\+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+PVD\+\_\+\+EXTI\+\_\+\+DISABLE\+\_\+\+EVENT}}()
\begin{DoxyCompactList}\small\item\em Disable event on PVD EXTI Line 16. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___p_w_r___exported___macro_ga7bef3f30c9fe267c99d5240fbf3f878c}{\+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+PVD\+\_\+\+EXTI\+\_\+\+ENABLE\+\_\+\+RISING\+\_\+\+EDGE}}()
\begin{DoxyCompactList}\small\item\em Enable the PVD Rising Interrupt Trigger. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___p_w_r___exported___macro_ga1ca8fd7f3286a176f6be540c75a004c6}{\+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+PVD\+\_\+\+EXTI\+\_\+\+DISABLE\+\_\+\+RISING\+\_\+\+EDGE}}()
\begin{DoxyCompactList}\small\item\em Disable the PVD Rising Interrupt Trigger. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___p_w_r___exported___macro_ga5b971478563a00e1ee1a9d8ca8054e08}{\+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+PVD\+\_\+\+EXTI\+\_\+\+ENABLE\+\_\+\+FALLING\+\_\+\+EDGE}}()
\begin{DoxyCompactList}\small\item\em Enable the PVD Falling Interrupt Trigger. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___p_w_r___exported___macro_ga1ca57168205f8cd8d1014e6eb9465f2d}{\+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+PVD\+\_\+\+EXTI\+\_\+\+DISABLE\+\_\+\+FALLING\+\_\+\+EDGE}}()
\begin{DoxyCompactList}\small\item\em Disable the PVD Falling Interrupt Trigger. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___p_w_r___exported___macro_ga638033d236eb78c1e5ecb9b49c4e7f36}{\+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+PVD\+\_\+\+EXTI\+\_\+\+ENABLE\+\_\+\+RISING\+\_\+\+FALLING\+\_\+\+EDGE}}()
\begin{DoxyCompactList}\small\item\em Enable the PVD Rising \& Falling Interrupt Trigger. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___p_w_r___exported___macro_ga3f66c9c0c214cd08c24674904dcdc4e0}{\+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+PVD\+\_\+\+EXTI\+\_\+\+DISABLE\+\_\+\+RISING\+\_\+\+FALLING\+\_\+\+EDGE}}()
\begin{DoxyCompactList}\small\item\em Disable the PVD Rising \& Falling Interrupt Trigger. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___p_w_r___exported___macro_ga5e66fa75359b51066e0731ac1e5ae438}{\+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+PVD\+\_\+\+EXTI\+\_\+\+GET\+\_\+\+FLAG}}()
\begin{DoxyCompactList}\small\item\em Check whether the specified PVD EXTI interrupt flag is set or not. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___p_w_r___exported___macro_gac0fb2218bc050f5d8fdb1a3f28590352}{\+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+PVD\+\_\+\+EXTI\+\_\+\+CLEAR\+\_\+\+FLAG}}()
\begin{DoxyCompactList}\small\item\em Clear the PVD EXTI flag. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___p_w_r___exported___macro_gaba4a7968f5c4c4ca6a7047b147ba18d4}{\+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+PVD\+\_\+\+EXTI\+\_\+\+GENERATE\+\_\+\+SWIT}}()
\begin{DoxyCompactList}\small\item\em Generates a Software interrupt on PVD EXTI line. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___p_w_r___p_v_d___e_x_t_i___line_ga43a49255649e03d2d2b6b12c5c379d2b}{PWR\+\_\+\+EXTI\+\_\+\+LINE\+\_\+\+PVD}}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga3bac4551decbfbbb98e8a5e19f526a39}{EXTI\+\_\+\+IMR1\+\_\+\+IM16}}
\item 
\#define \mbox{\hyperlink{group___p_w_r___i_s___p_w_r___definitions_gabac4485a57abc97aad91eaa0b65ae927}{IS\+\_\+\+PWR\+\_\+\+PVD\+\_\+\+LEVEL}}(LEVEL)
\item 
\#define \mbox{\hyperlink{group___p_w_r___i_s___p_w_r___definitions_ga8edfbbba20e58a9281408c23dc6ff7ef}{IS\+\_\+\+PWR\+\_\+\+PVD\+\_\+\+MODE}}(MODE)
\item 
\#define \mbox{\hyperlink{group___p_w_r___i_s___p_w_r___definitions_ga03c105070272141c0bab5f2b74469072}{IS\+\_\+\+PWR\+\_\+\+REGULATOR}}(REGULATOR)
\item 
\#define \mbox{\hyperlink{group___p_w_r___i_s___p_w_r___definitions_ga9b36a9c213a77d36340788b2e7e277ff}{IS\+\_\+\+PWR\+\_\+\+SLEEP\+\_\+\+ENTRY}}(ENTRY)
\item 
\#define \mbox{\hyperlink{group___p_w_r___i_s___p_w_r___definitions_ga4a94eb1f400dec6e486fbc229cbea8a0}{IS\+\_\+\+PWR\+\_\+\+STOP\+\_\+\+ENTRY}}(ENTRY)
\item 
\#define \mbox{\hyperlink{group___p_w_r___i_s___p_w_r___definitions_gab7f9039ed34cc5af3d57606c726e66a2}{IS\+\_\+\+PWR\+\_\+\+REGULATOR\+\_\+\+VOLTAGE}}(VOLTAGE)
\end{DoxyCompactItemize}
\doxysubsubsection*{Functions}
\begin{DoxyCompactItemize}
\item 
void {\bfseries HAL\+\_\+\+PWR\+\_\+\+De\+Init} (void)
\item 
void {\bfseries HAL\+\_\+\+PWR\+\_\+\+Enable\+Bk\+Up\+Access} (void)
\item 
void {\bfseries HAL\+\_\+\+PWR\+\_\+\+Disable\+Bk\+Up\+Access} (void)
\item 
void {\bfseries HAL\+\_\+\+PWR\+\_\+\+Config\+PVD} (const \mbox{\hyperlink{struct_p_w_r___p_v_d_type_def}{PWR\+\_\+\+PVDType\+Def}} \texorpdfstring{$\ast$}{*}s\+Config\+PVD)
\item 
void {\bfseries HAL\+\_\+\+PWR\+\_\+\+Enable\+PVD} (void)
\item 
void {\bfseries HAL\+\_\+\+PWR\+\_\+\+Disable\+PVD} (void)
\item 
void {\bfseries HAL\+\_\+\+PWR\+\_\+\+Enable\+Wake\+Up\+Pin} (uint32\+\_\+t Wake\+Up\+Pin\+Polarity)
\item 
void {\bfseries HAL\+\_\+\+PWR\+\_\+\+Disable\+Wake\+Up\+Pin} (uint32\+\_\+t Wake\+Up\+Pinx)
\item 
void {\bfseries HAL\+\_\+\+PWR\+\_\+\+Enter\+STOPMode} (uint32\+\_\+t Regulator, uint8\+\_\+t STOPEntry)
\item 
void {\bfseries HAL\+\_\+\+PWR\+\_\+\+Enter\+SLEEPMode} (uint32\+\_\+t Regulator, uint8\+\_\+t SLEEPEntry)
\item 
void {\bfseries HAL\+\_\+\+PWR\+\_\+\+Enter\+STANDBYMode} (void)
\item 
void {\bfseries HAL\+\_\+\+PWR\+\_\+\+PVD\+\_\+\+IRQHandler} (void)
\item 
void {\bfseries HAL\+\_\+\+PWR\+\_\+\+PVDCallback} (void)
\item 
void {\bfseries HAL\+\_\+\+PWR\+\_\+\+Enable\+Sleep\+On\+Exit} (void)
\item 
void {\bfseries HAL\+\_\+\+PWR\+\_\+\+Disable\+Sleep\+On\+Exit} (void)
\item 
void {\bfseries HAL\+\_\+\+PWR\+\_\+\+Enable\+SEVOn\+Pend} (void)
\item 
void {\bfseries HAL\+\_\+\+PWR\+\_\+\+Disable\+SEVOn\+Pend} (void)
\end{DoxyCompactItemize}


\doxysubsection{Detailed Description}
Header file of PWR HAL module. 

\begin{DoxyAuthor}{Author}
MCD Application Team 
\end{DoxyAuthor}
\begin{DoxyAttention}{Attention}

\end{DoxyAttention}
Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-\/\+IS. 